In the field of integrated circuit (IC) fabrication, technology scaling continues; i.e., the size of circuit features continues to decrease. With technology scaling, process imperfections result in deviation of actual on-wafer patterns from the designed circuit layout. To fabricate a layout, each wafer has to go through patterning of several layers to fabricate transistors, contacts and interconnects. A tool has to physically pick a mask and align it with the wafer to fabricate the desired pattern. With minimum feature size on a wafer scaled to less than 30 nm, the alignment tolerance is typically reduced to less than 5 nm for several significant layers. Static Random Access Memories (SRAMs) are an example of a type of circuit that is particularly vulnerable to this kind of impact. This is due to the extremely dense layouts and very stringent ground rules associated with SRAMs.